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Beam Me Up, Scotty, There's a Teraflop Monster Here!

Intel is going to have itself a general-purpose 'Teraflops' chip in a few years

Well, if it can make it x86-compatible, get somebody to write a workable operating system for it, teach the world a new way of parallel computing-style programming, and produce it in volume, Intel is going to have itself a general-purpose "Teraflops" chip in a few years.

The company has so far managed a "shock and awe" 80-core research prototype that it unveiled this week for all to gaze on in admiration at the Integrated Solid State Circuits Conference (ISSCC) in San Francisco. The disclosure is considered an industry proof-point.

It puts the power of ASCI Red, the 10,000 Pentium Pro-based system that Intel deployed at the Sandia National Lab 10 years ago on a single sliver of silicon the size of your fingernail.

ASCI Red took up more than 2,000 square feet and ate up 500 kilowatts of electricity.

The new 65nm 3.16GHz supercomputer chip, capable of one trillion calculations a second, runs full blast at only 62W - less than many single-core processors today - and Intel imagines it delivering high-definition entertainment on PCs, servers and handhelds and breaking new ground in everyday artificial intelligence, instant video communications, photo-realistic games, multimedia data mining and real-time speech recognition.

The chip Intel showed off - and it resists any comparisons to the Cell - isn't expected to be commercialized, but some variant of it, with more or less cores, is in the next five or 10 years.

Intel has something like a hundred internal tera-scale projects working towards that end - including making it x86 - and they sorta, kinda have to make it happen because it's been established that multi-core performance degrades the other side of 16 cores, Intel said.

Anyway, the approach Intel has taken isn't multi-core in any way multi-core has been expressed so far. It's using what it calls "tiles" instead, little tiny replicated rectangle "lozenges" to make it easier to design a many-core chip.

The Teraflop chip, code named Polaris, also features a mesh-like "network-on-a-chip" for super-high bandwidth communications between the cores, capable of moving 80 billion bytes of data a second inside the chip.

The scalable tiles, each of which has its own router connecting it to adjacent tiles, divide up a problem and together return the answer. They can also be independently powered down.

Intel is mating memory chips directly to the tiles to move data between processor and memory practically instantaneous.

Elsewhere in multi-core land Sun has eight cores on its T1 Sparc, Azul has 48 heads on its special-purpose Java-specific chips and ClearSpeed has put 96 cores on its co-processor accelerator. AMD is going down the road of integrating the graphic processor with the CPU complements of its $5.4 billion ATI acquisition.

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SYS-CON's Security News desk trawls the world of security for news of software, hardware, products, and services that seems likely to be of interest to infosec professionals and summarizes them for easy assimilation by busy IT managers and staff.

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